LCMXO2-1200UHC-4FTG256I Field Programmable Gate Array (FPGA) IC 79 65536 1280

Features of LCMXO2-1200UHC-4FTG256I

Administrator:
• On-Chip User Flash Memory
• Up to 256 kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2C and JTAG interfaces
• Can be used as soft processor PROM or as Flash memory
• Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with DQS support
• High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5 V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
• Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)
• Up to two analog PLLs per device with fractional-n frequency synthesis
– Wide input frequency range (7 MHz to 400 MHz)
• Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I2C
• Supports background programming of non-volatile memory
• Optional dual boot with external SPI memory
• TransFR™ Reconfiguration
• In-field logic update while system operates

Applications of LCMXO2-1200UHC-4FTG256I

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically.

Environmental & Export Classifications of LCMXO2-1200UHC-4FTG256I