DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
■ Compatible with JEDEC-standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
■ Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■ Minimum 100,000 write/erase cycles guaranteed
■ High performance
— 55 ns maximum access time
■ Sector erase architecture
— Uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
Also supports full chip erase.
■ Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations
■ Embedded Erase Algorithms
— Automatically preprograms and erases the chip
or any combination of sectors
■ Embedded Program Algorithms
— Automatically programs and verifies data at
specified address
■ Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
■ Erase suspend/resume
— Supports reading data from a sector not being
erased
■ Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
■ Enhanced power management for standby
mode
— <1 µA typical standby current
— Standard access time from standby mode
Flexible Sector-Erase Architecture
■ Eight 64 Kbyte sectors
■ Individual-sector, multiple-sector, or bulk-erase
capability
■ Individual or multiple-sector protection is user
definable