Platform Flash In-System Programmable Configuration PROMs

Features
• In-System Programmable PROMs for Configuration of Xilinx® FPGAs
• Low-Power Advanced CMOS NOR Flash Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range (–40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
• I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V
• Design Support Using the Xilinx ISE® Alliance and Foundation™ Software Packages
• XCF01S/XCF02S/XCF04S
♦ 3.3V Supply Voltage
♦ Serial FPGA Configuration Interface
♦ Available in Small-Footprint VO20 and VOG20 Packages
• XCF08P/XCF16P/XCF32P
♦ 1.8V Supply Voltage
♦ Serial or Parallel FPGA Configuration Interface
♦ Available in Small-Footprint VO48, VOG48, FS48, and FSG48 Packages
♦ Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for Configuration
♦ Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology

Absolute Maximum Ratings

Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can undershoot to –2.0V or overshoot to +7.0V, provided this overshoot or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.

Supply Voltage Requirements for Power-On Reset and Power-Down

Notes:
1. V_CCINT, V_CCO, and V_CCJ supplies can be applied in any order.
2. At power up, the device requires the V_CCINT power supply to monotonically rise to the nominal operating voltage within the specified T_VCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly.
3. If the V_CCINT and V_CCO supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released, then the configuration data from the PROM is not available at the recommended threshold levels. The configuration sequence must be delayed until both V_CCINT and V_CCO have reached their recommended operating conditions.