NDS9952A
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N- and P-channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
Features
Absolute Maximum Ratings TA= 25°C unless otherwise noted
Symbol | Parameter | N-Channel | P-Channel | Units |
VDSS | Drain-Source Voltage | 30 | -30 | V |
VGSS | Gate-Source Voltage | ± 20 | ± 20 | V |
ID | Drain Current - Continuous (Note 1a) - Pulsed | ± 3.7 | ± 2.9 | A |
± 15 | ± 150 | |||
PD | Power Dissipation for Dual Operation | 2 | W | |
Power Dissipation for Single Operation (Note 1a) (Note 1b) (Note 1c) | 1.6 | |||
1 | ||||
0.9 | ||||
TJ ,TSTG | Operating and Storage Temperature Range | -55 to 150 | °C |
Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78℃/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125℃/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135℃/W when mounted on a 0.003 in2 pad of 2oz cpper.
Scale 1 : 1 on letter size paper
Stock Offer (Hot Sell)
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