AM3352BZCZ30 AM3352BZCZD80 AM3354BZCZA100 AM3354BZCZD80 Microcontroller Integrated Circuit MPU Sitara ARM Cortex-A8 MPU

1 Features

• Up to 1-GHz SitaraTM ARM® Cortex®-A8 32‐Bit RISC Processor

  • – NEONTM SIMD Coprocessor

  • – 32KB of L1 Instruction and 32KB of Data Cache

    With Single-Error Detection (Parity)

  • – 256KB of L2 Cache With Error Correcting Code

    (ECC)

  • – 176KB of On-Chip Boot ROM

  • – 64KB of Dedicated RAM

  • – Emulation and Debug - JTAG

  • – Interrupt Controller (up to 128 Interrupt

    Requests)

• On-Chip Memory (Shared L3 RAM)

  • – 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM

  • – Accessible to All Masters

  • – Supports Retention for Fast Wakeup

• External Memory Interfaces (EMIF)

  • – mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:

    • – mDDR: 200-MHz Clock (400-MHz Data Rate)

    • – DDR2: 266-MHz Clock (532-MHz Data Rate)

    • – DDR3: 400-MHz Clock (800-MHz Data Rate)

    • – DDR3L: 400-MHz Clock (800-MHz Data

      Rate)

    • – 16-Bit Data Bus

    • – 1GB of Total Addressable Space

    • – Supports One x16 or Two x8 Memory Device

      Configurations

  • – General-Purpose Memory Controller (GPMC)

    • – Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)

    • – Uses BCH Code to Support 4-, 8-, or 16-Bit ECC

    • – Uses Hamming Code to Support 1-Bit ECC

  • – Error Locator Module (ELM)

    • – Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm

    • – Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms

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