DS1232LP+ Low Power MicroMonitor Chip

FEATURES

Super low-power version of DS1232

50
A quiescent current

Halts and restarts an out–of–control microprocessor

Automatically restarts microprocessor after power failure

Monitors pushbutton for external override

Accurate 5% or 10% microprocessor power supply monitoring 8–pin DIP, 8–pin SOIC or space saving µ–SOP package available

Optional 16–pin SOIC package available

Industrial temperature –40°C to +85°C available, designated N

DESCRIPTION

The DS1232LP/LPS Low Power MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply, software execution, and external override. First, a precision temperature–compensated reference and comparator circuit monitors the status of VCC. When an out–of–tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize.

The second function the DS1232LP/LPS performs is pushbutton reset control. The DS1232LP/LPS debounces the pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a watchdog timer. The DS1232LP/LPS has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to time–out. The watchdog timer function can be set to operate on timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds.

OPERATION – POWER MONITOR

The DS1232LP/LPS detects out–of–tolerance power supply conditions and warns a processor–based system of impending power failure. When VCC falls below a preset level as defined by TOL, the VCC comparator outputs the signals RST and RST. When TOL is connected to ground, the RST and RST signals become active as VCC falls below 4.75 volts. When TOL is connected to VCC, the RST and RST signals become active as VCC falls below 4.5 volts. The RST and RST are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid VCC. On power–up, RST and RST are kept active for a minimum of 250 ms to allow the power supply and processor to stabilize. OPERATION – PUSHBUTTON RESET The DS1232LP/LPS provides an input pin for direct connection to a pushbutton (Figure 1). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that RST and RST signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level.

OPERATION – WATCHDOG TIMER

The watchdog timer function forces RST and RST signals to the active state when the ST input is not stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to VCC. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive. If a high–to–low transition occurs on the ST input pin prior to time–out, the watchdog timer is reset and begins to time–out again. If the watchdog timer is allowed to time-out, then the RST and RST signals are driven to the active state for 250 ms minimum. The ST input can be derived from microprocessor address signals, data signals, and/or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to time–out. To guarantee that the watchdog timer does not time–out, a high–to– low transition must occur at or less than the minimum shown in Table 1. A typical circuit example is shown in Figure 2.

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