128M-BIT [x 1] CMOS SERIAL FLASH

GENERAL

• Serial Peripheral Interface compatible -- Mode 0 and Mode 3

• 134,217,728 x 1 bit structure

• 4096 equal sectors with 4K byte each 256 equal sectors with 64K byte each

- Any sector can be erased

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE

• High Performance - Fast access time: 50MHz serial clock (30pF + 1TTL Load)

- Fast program time: 1.4ms/page (typical, 256-byte per page) and 9us/byte (typical)

- Fast erase time: 60ms/sector (4KB per sector), 0.7s/block (64KB per block) and 80s/chip

- Acceleration mode:

- Chip erase time: 50s (typical)

• Low Power Consumption

- Low active read current: 25mA (max.) at 50MHz

- Low active programming current: 20mA (max.)

- Low active erase current: 20mA (max.)

- Low standby current: 20uA (max.)

- Deep power-down mode 20uA (max.)

• Typical 100,000 erase/program cycle

• 10 years data retention

SOFTWARE FEATURES

• Input Data Format - 1-byte Command code

• Advanced Security Features

- Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions

- Additional 512-bit secured OTP for unique identifier

• Auto Erase and Auto Program Algorithm

- Automatically erases and verifies data at selected sector

- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)

• Status Register Feature

• Electronic Identification

- JEDEC 1-byte manufacturer ID and 2-byte Device ID

- RES command, 1-byte Device ID

- REMS command, ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first

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