FAN7530
Critical Conduction Mode PFC Controller
Features
Applications
Related Application Notes
Description
The FAN7530 is an active power factor correction (PFC) controller for boost PFC applications that operates in critical conduction mode (CRM). It uses the voltage mode PWM that compares an internal ramp signal with the error amplifier output to generate MOSFET turn-off signal. Since the voltage mode CRM PFC controller does not need rectified AC line voltage information, it saves the power loss of the input voltage sensing network necessary for the current mode CRM PFC controller.
FAN7530 provides many protection functions, such as over voltage protection, open-feedback protection, overcurrent protection, and under-voltage lockout protection. The FAN7530 can be disabled if the INV pin voltage is lower than 0.45V and the operating current decreases to 65µA. Using a new variable on-time control method, THD is lower than the conventional CRM boost PFC ICs.
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. TA=25°C, unless otherwise specified.
Symbol | Parameter | Value | Unit |
VCC | Supply Voltage | VZ | V |
IOH, IOL | Peak Drive Output Current | +500/-800 | mA |
Iclamp | Driver Output Clamping Diodes VO>VCC or VO<-0.3V | ±10 | mA |
Idet | Detector Clamping Diodes | ±10 | mA |
VIN | Error Amplifier, MOT, CS Input Voltages | -0.3 to 6 | V |
TJ | Operating Junction Temperature | 150 | °C |
TA | Operating Temperature Range | -40 to 125 | °C |
TSTG | Storage Temperature Range | -65 to 150 | °C |
VESD_HBM | ESD Capability, Human Body Model | 2.0 | kV |
VESD_MM | ESD Capability, Machine Model | 300 | V |
VESD_CDM | ESD Capability, Charged Device Model | 500 | V |
Typical Application Diagrams
Figure 1. Typical Boost PFC Application
Internal Block Diagram
Figure 2. Functional Block Diagram of FAN7530
Pin Assignments
Figure 3. Pin Configuration (Top View)