Microwave Integrated Circuits CLC001AJE Serial Digital Cable Driver

CLC001 Serial Digital Cable Driver with Adjustable Outputs

General Description

The CLC001 is a monolithic, high-speed cable driver designed for use in SMPTE 259M serial digital video and ITU-T G.703 serial digital data transmission applications. The CLC001 drives 75Ω transmission lines (Belden 8281 or equivalent) at data rates up to 622 Mbps. Controlled output rise and fall times (400 ps typical) minimize transitioninduced jitter. The output voltage swing is adjustable from 800 mVp-p to 1.0 Vp-p using an external resistor.

The CLC001’s output stage consumes less power than other designs. The differential inputs accept LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. All these make the CLC001 an excellent general purpose high speed driver for high-speed, long distance data transmission applications.

The CLC001 is powered from a single +3.3V supply and comes in a small 8-pin SOIC package.

Key Specifications

n 400 ps rise and fall times

n Data rates to 622 Mbps

n 100 mV differential input threshold

n Low residual jitter

Applications

n Digital routers and distribution amplifiers

n Coaxial cable driver for digital transmission lines

n Twisted pair driver

n Serial digital video interfaces for the commercial and broadcast industry

n SMPTE, Sonet/SDH, and ATM compatible driver

n Buffer applications

Typical Application

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VSS = 0V.

Note 3: Typical values are at 25˚C and 3.3V.

Note 4: This parameter is Guaranteed by Design.

Note 5: RL = 75Ω, AC-coupled at 270 Mbps, RREF = 1.91 kΩ 1% (for VSDO = 800 mVp-p ±10%), CL not greater than 5pF (See Figure 1)

Note 6: The VBB output is intended as a bias supply pin for the inputs of this device only. It is not designed as a power supply output and should not be used to power other devices.

Note 7: RL = 75Ω, AC-coupled at 622 Mbps, RREF = 1.5 kΩ 1% (for VSDO = 1.0 Vp-p ±10%), clock pattern input.

Note 8: Input Current Balance (IINB) is the difference between the Input Current (IIN) on VIN+ and VIN− for the same bias condition