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Supply Ability :
220 pcs
Delivery Time :
3-5 Day
Packaging Details :
International Standard Packaging
Category :
Field Programmable Gate Array
Condition :
Original 100%,Brand New and Original,New
Number of Logic Array Blocks - LABs :
14144
Number of I/Os :
488 I/O
Package / Case :
BGA-780
Operating Supply Voltage :
900 mV
Series :
Stratix IV E
Maximum Operating Frequency :
600 MHz
Service :
BOM Kitting
Lead time :
In Stock,contact us
Description
EP4SE360H29C4N Field Programmable Gate Array Stratix IV E
Product Attribute
Attribute Value
Intel
FPGA - Field Programmable Gate Array
Stratix IV E
353600
14144
488 I/O
900 mV
0 C
+ 70 C
SMD/SMT
BGA-780
Tray
Series:
Stratix IV
Brand:
Intel / Altera
Maximum Operating Frequency:
600 MHz
Moisture Sensitive:
Yes
Product Type:
FPGA - Field Programmable Gate Array
Factory Pack Quantity:
24
Subcategory:
Programmable Logic ICs
Total Memory:
22564 kbit
Tradename:
Stratix
Part # Aliases:
973234
Stratix IV E
■ Up to 16 global clocks and 88 regional clocks optimally routed to meet the maximum performance of 800 MHz ■ Up to 112 and 132 periphery clocks in Stratix IV GX and Stratix IV E devices, respectively ■ Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in Stratix IV GX and Stratix IV GT devices ■ Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in Stratix IV E devices ■ Dedicated circuitry on the left and right sides of the device to support differential links at data rates from 150 Mbps to 1.6 Gbps ■ Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT devices ■ DPA circuitry at the receiver automatically compensates for channel-to-channel and channel-to-clock skew in source synchronous interfaces ■ Soft-CDR circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clocks at up to 1.6 Gbps data rate (SGMII and GbE) ■ Stratix IV E devices provide an excellent solution for applications that do not require high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive.