• Powerful clock management tile (CMT) clocking − Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting − PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
• System Monitoring capability on all devices − On-chip/Off-chip thermal monitoring − On-chip/Off-chip power supply monitoring − JTAG access to all monitored quantities
• Integrated Endpoint blocks for PCI Express Designs − LXT, SXT, TXT, and FXT Platforms − Compliant with the PCI Express Base Specification 1.1 − x1, x4, or x8 lane support per block − Works in conjunction with RocketIO™ transceivers
Virtex®-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. Virtex-5 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.