• Create FPGA-based HPC platforms and in-socket accelerators • Up to 2M logic cell capacity for massively parallel processing • Thousands of DSP48E slices for fixed- and floating-point acceleration • Up to 64.8Mb of integrated Block RAM to move operand and result data at Tbps bandwidths • Support for multiple DDR3 memory subsystems for high-bandwidth data buffering • Up to 96 high-speed serial transceivers in a single device for processor and inter-FPGA communication; PCIe Gen3 support offers additional CPU interface options • Enhanced support for QPI for low-latency, cache-coherent, high-bandwidth CPU interfaces • 10GE support for advanced network interfaces
The Strength of a Scalable Optimized Architecture All 7 series FPGA families leverage the Xilinx scalable, optimized architecture to protect IP investments and make it easy to migrate 6 series designs. With common elements including logic fabric, block RAM, DSP engines, clocking, Analog Mixed Signal (AMS) capability, and more, the scalable, optimized architecture also facilitates rapid retargeting within the 7 series. For design migrations and new projects alike, the Virtex-7 architecture dramatically reduces development times and lets designers focus on product differentiation.