2.0mm HDI PCBs for LPDDR4 Socket Interposer stack up 4-2-4 immersion gold

1 . Descriptions:

What is the PCB Layout Changes Needed for DDR4 Implementation?

DDR4 or Double Data Rate 4 comes in two distinct module types. So-DIMM or small outline dual in-line memory modules (260-pins) that are in use in portable computing devices like laptops. The other module type is DIMM or dual in-line memory modules (288-pins) that are in use in devices like desktops and servers.

So, the first change in architecture is, of course, due to the pin count. The previous iteration (DDR3) uses 240-pins for a DIMM and 204-pins for a So-DIMM. Whereas the previously mentioned, DDR4 uses 288-pins for its DIMM application. With the increase in pins or contacts, DDR4 offers higher DIMM capacities, enhanced data integrity, faster download speed, and an increase in power efficiency.

Accompanying this overall improvement in performance is also a curved design (bottom) that enables better, more secure attachment, and it improves stability and strength during installation. Also, there are bench tests that confirm that DDR4 offers a 50% increase in performance and can achieve up to 3,200 MTs (Mega Transfers per Second).

Furthermore, it achieves these increases in performance in spite of using less power; 1.2 volts (per DIMM) instead of the 1.5 to 1.35-volt requirement of its predecessor. All of these changes mean that the PCB designers must reassess their design approach for the implementation of DDR4.

2 . Specifications:

Double-Data Rate, or DDR memory is very common in printed circuit board design today. Many designs will use some version of this memory configuration which requires specific routing patterns in the layout. DDR gets its name from its ability to send and receive signals twice per clock cycle, which is double the rate of the original Single Data Rate (SDR) memory. Because of this doubled rate, the trace routing for DDR memory must hold tighter parameters in order to meet the performance specifications.

The key to designing memory circuitry is in meeting its timing specifications. Each signal needs to be timed so that the data can be captured on the rising and falling edge of the associated clock signal. As the data rates increase with each new iteration of DDR memory, the timing margins will become narrower. This is where precise routing patterns are needed in order to fulfill the timing requirements.