Altera EP4CE75F23I7N Ic Chip Programming Cyclone IV FPGA Device 292 I/O 4713 LAB 2745 Kbit

Specifications

Description

Altera’s new Cyclone® IV FPGA device family extends the Cyclone FPGA series leadership in providing

the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are

targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing

bandwidth requirements while lowering costs. Built on an optimized low-power process, the Cyclone IV

device family offers the following two variants:

■ Cyclone IV E—lowest power, high functionality with the lowest cost

■ Cyclone IV GX—lowest power and lowest cost FPGAs with 3.125 Gbps transceivers 1 Cyclone IV E

devices are offered in core voltage of 1.0 V and 1.2 V. f For more information, refer to the Power

Requirements for Cyclone IV Devices chapter. Providing power and cost savings without sacrificing

performance, along with a low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost,

small-form-factor applications in the wireless, wireline, broadcast, industrial, consumer, and communications

industries.

Features

The Cyclone IV device family offers the following features:

Low-cost, low-power FPGA fabric:

6K to 150K logic elements

Up to 6.3 Mb of embedded memory

Up to 360 18 × 18 multipliers for DSP processing intensive applications

Protocol bridging applications for under 1.5 W total power

Cyclone IV GX devices offer up to eight high-speed transceivers that provide:

Data rates up to 3.125 Gbps

8B/10B encoder/decoder

8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface

Byte serializer/deserializer (SERDES)

Word aligner

Rate matching FIFO

TX bit slipper for Common Public Radio Interface (CPRI)

Electrical idle

Dynamic channel reconfiguration allowing you to change data rates and protocols on-the-fly

Static equalization and pre-emphasis for superior signal integrity

150 mW per channel power consumption

Flexible clocking structure to support multiple protocols in a single transceiver block

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