Programmable Integrated Circuits 10M08SAU169C8G Intel MAX10 FPGA Device

Specifications

Description

Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process technology Packaging

• Low cost, small form factor packages—support multiple packaging technologies and pin pitches

• Multiple device densities with compatible package footprints for seamless migration between different

device densities

• RoHS6-compliant Core architecture

• 4-input look-up table (LUT) and single register logic element (LE)

• LEs arranged in logic array block (LAB)

• Embedded RAM and user flash memory

• Clocks and PLLs

• Embedded multiplier blocks

• General purpose I/Os Internal memory blocks

• M9K—9 kilobits (Kb) memory blocks

• Cascadable blocks to create RAM, dual port, and FIFO functions User flash memory (UFM)

• User accessible non-volatile storage

• High speed operating frequency

• Large memory size

• High data retention

• Multiple interface option Embedded multiplier blocks

• One 18 × 18 or two 9 × 9 multiplier modes

• Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines ADC

• 12-bit successive approximation register (SAR) type

• Up to 17 analog inputs

• Cumulative speed up to 1 million samples per second ( MSPS)

• Integrated temperature sensing capability Clock networks

• Global clocks support

• High speed frequency in clock network Internal oscillator Built-in internal ring oscillator PLLs

• Analog-based

• Low jitter

• High precision clock synthesis

• Clock delay compensation

• Zero delay buffering

• Multiple output taps General-purpose I/Os (GPIOs)

• Multiple I/O standards support

• On-chip termination (OCT)

• Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter External memory

interface (EMIF) (1) Supports up to 600 Mbps external memory interfaces:

Features

Ordering Code and Available Options for Intel MAX 10 Devices

Trading Guide