Quick Detail:

The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated onadvanced CMOS technology

Description:

Altera EP910 devices can implement up to 450 usable gates of SSI and MSI logic functions. EP910 devices have 24 macrocells, 12 dedicated input pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 and CLK2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively.

Applications:

■ High-performance, 24-macrocell Classic EPLD

– Combinatorial speeds with tPD as fast as 12 ns

– Counter frequencies of up to 76.9 MHz

– Pipelined data rates of up to 125 MHz

■ Programmable I/O architecture with up to 36 inputs or 24 outputs

■ EP910 and EP910I devices are pin-, function-, and programming filecompatible

■ Programmable clock option for independent clocking of all registers

■ Macrocells individually programmable as D, T, JK, or SR flipflops, or

for combinatorial operation

■ Available in the following packages (see Figure 11)

– 44-pin plastic J-lead chip carrier (PLCC)

– 40-pin ceramic and plastic dual in-line packages (CerDIP and PDIP)

Specifications:

Competitive Advantage:

Warranty :180days for all goods

Free shipping:Order over $600 win a free shipment fee:goods weight below 3Kg.

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