Quick Detail:

Second-Generation 32-Bit Enhanced Embedded Controller

Description:

The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the 32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with accesses to the internal caches and the bus controller.

The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030 as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for offchip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the average access time for operand fetches is minimized.

The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM) memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the

MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure1) provides the precise clock signals required to efficiently control memory subsystems, eliminating system design constraints due to clock generation and distribution.

Applications:

• Complete 32-Bit Nonmultiplexed Address and Data Buses

• Sixteen 32-Bit General-Purpose Data and Address Registers

• Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers

• Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection

• Pipelined Architecture with Increased Parallelism Allows:

– Internal Caches Accesses in Parallel with Bus Transfers

– Overlapped Instruction Execution

• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),

Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)

• Complete Support for Coprocessors with the M68000 Coprocessor Interface

• Internal Status Indication for Hardware Emulation Support

• 4-Gbyte Direct Addressing Range

• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size

Specifications:

Competitive Advantage:

Warranty :180 days !
Free shipping: Order over $1000 win a free shipment fee
(goods weight below 3Kg) ,during 20130901-20130930 .

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