SAK-TC233LP-32F200F TriCore™ - Microcontroller IC 32-Bit Single-Core 200MHz 2MB (2M X 8) FLASH PG-TQFP-100-23

Datasheet:SAK-TC233LP-32F200F

Features:

The TC23x product family has the following features:

• High Performance Microcontroller with one CPU core • Power Efficient scalar TriCore CPU (TC1.6E), having the following features: – Binary code compatibility with TC1.6P – up to 200 MHz operation at full temperature range – up to 184 Kbyte Data Scratch-Pad RAM (DSPR) – up to 8 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 8 Kbyte Instruction Cache (ICACHE)

– 4 line read buffer (DRB)

• Lockstepped shadow core for TC1.6E

• Multiple on-chip memories

– All embedded NVM and SRAM are ECC protected

– up to 2 Mbyte Program Flash Memory (PFLASH)

– up to 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 32 Kbyte Memory (LMU)

– 512 Kbyte Memory (EMEM)

– BootROM (BROM)

• 16-Channel DMA Controller with safe data transfer

• Sophisticated interrupt system (ECC protected)

• High performance on-chip bus structure

– 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

• Optional Hardware Security Module (HSM) on some variants (See below)

• Safety Management Unit (SMU) handling safety monitor alarms

• Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)

• Hardware I/O Monitor (IOM) for checking of digital I/O

• Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud

– Four Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s

– Two MultiCAN+ Module with 3CAN nodes each and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfe

r – 4 Single Edge Nibble Transmission (SENT) channels for connection to sensors

– One FlexRayTM module with 2 channels (E-Ray) supporting V2.1

– One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

– One Capture / Compare 6 module (Two kernels CCU60 and CCU61)

– One General Purpose 12 Timer Unit (GPT120)

– IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)

• Versatile Successive Approximation ADC (VADC)

– Cluster of 4 independent ADC kernels

– Input voltage range from 0 V to 5.5V (ADC supply)

• Digital programmable I/O ports

• On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)

• Four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface

• Power Management System and on-chip regulators

• Clock Generation Unit with System PLL and Flexray PLL

• Embedded Voltage Regulator

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