Intel | |
Product Category: | FPGA - Field Programmable Gate Array |
RoHS: | Details |
Arria 10 GX 160 | |
160000 LE | |
61510 ALM | |
9.85 Mbit | |
288 I/O | |
870 mV | |
980 mV | |
0 C | |
+ 100 C | |
17.4 Gb/s | |
12 Transceiver | |
SMD/SMT | |
FBGA-780 | |
Tray | |
Brand: | Intel / Altera |
Maximum Operating Frequency: | 1.5 GHz |
Moisture Sensitive: | Yes |
Operating Supply Voltage: | 950 mV |
Product Type: | FPGA - Field Programmable Gate Array |
Subcategory: | Programmable Logic ICs |
Tradename: | Arria 10 FPGA |
Part # Aliases: | 966320 |
The Intel® Arria® 10 device family consists of high-performance and power-efficient
20 nm mid-range FPGAs and SoCs.
Intel Arria 10 device family delivers:
• Higher performance than the previous generation of mid-range and high-end FPGAs.
• Power efficiency attained through a comprehensive set of power-saving technologies.
The Intel Arria 10 devices are ideal for high performance, power-sensitive, midrange
applications in diverse markets.
Applications
Wireless
●Channel and switch cards in remote radio heads
Mobile backhaul
Wireline
●40G/100G muxponders and transponders
●100G line cards
●Bridging
Aggregation
Broadcast
Studio switches
Servers and transport
●Videoconferencing
●Professional audio and video
Computing and Storage
●Flash cache
●Cloud computing servers
●Server acceleration
Medical
●Diagnostic scanners
Diagnostic imaging
Military
●Missile guidance and control
●Radar
●Electronic warfare
●Secure communications
Feature
Technology
●TSMC's 20-nm SoC process technology
●Allows operation at a lower Vcc level of 0.82 V instead of the 0.9 Vstandard Vcc core voltage
Packaging
●1.0 mm ball-pitch Fineline BGA packaging
0.8 mm ball-pitch Ultra Fineline BGA packaging
●Multiple devices with identical package footprints for seamless migration between different
FPGA densities
Devices with compatible package footprints allow migration to next generation high-end
Stratixo 10 devices
RoHS, leaded(1), and lead-free (Pbr-free) options
High-performance
●Enhanced 8-input ALM with four registers
FPGA fabric
●Improved multi-track routing architecture to reduce congestion and improve compilation time
●Hierarchical core docking architecture
Fine-grained partlal reconfiguration
Internal memory
M20K- 20-Kb memory blocks with hard error correction code (ECC)
blocks
●Memory logic array block (MLAB)- 640-bit memory
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