7" Inch 1024x600 LVDS TFT LCD with CTP, PCAP Touch Screen 7 inch IPS Product Introduction

Product Quick Details:

1. LCD Size: 7” inch TFT
2. Resolution: 1024x600
3. Viewing Angle: Free
4. Outline Dimension: 165x100x5.7mm
5. LCM Interface Type: LVDS

6. CTP Interface Type: I2C
7. Temperature: Top -20°C to +70°C; Tst -30°C to +80°C
8. Touch Panel: Capacitive Touch Screen(CTP)

SAEF Technology ZDX070BIV1-B3 is a 7”inch IPS type full viewing angle TFT LCD Display with resolution of 1024x600 pixels. It is with Capacitive Touch Screen(CTP), and the cover glass is customizable.

This LCD module is has outline dimension of 165x100x5.7mm, and AA size of 154.2144(H) ×85.92(V) mm. This 7" TFT LCD is with PCAP(Capacitive Touch Screen). ZDX070BIV1-B3 LCM interface is with LVDS interface, 30 pins. The CTP interface is I2C. ZDX070BIV1-B3 is with 300cd/m2 (nits) surface brightness, this LCD Display Module can be operating at temperatures from –20℃ to +70℃.

This 7” TFT LCD module is widely used in measuring equipment, medical device, home automation, access security system, supermarket price tag, and household appliances, GPS device, etc.

7" Inch 1024x600 LVDS TFT LCD with CTP, PCAP Touch Screen 7 inch IPS Product Drawing

7" Inch 1024x600 LVDS TFT LCD with CTP, PCAP Touch Screen 7 inch IPS Product Image

Facilities and Certificates

What's LVDS

LVDS (Low Voltage Differential Signaling): It is a low-voltage differential signaling technology interface. It is a digital video signal transmission method developed by NS Corporation (National Semiconductor Corporation) in the United States to overcome the shortcomings of high power consumption and EMI electromagnetic interference when transmitting broadband and high bit rate data in TTL level.

In recent years, with the rapid development of the electronics industry, intelligent display equipment has also made brilliant achievements, and high-definition display has been favored by consumers. At present, the high-definition display protocol interfaces include RGB, LVDS, MIPI, eDP, HDMI, miniLVDS, V-by-One, etc

The LVDS level standard uses a pair (two) of differential signal lines to transmit data.

By driving a 3.5mA stable current supply, data can be transmitted at high speed with a very low amplitude differential signal of 350mV at the 100Ω termination. The data transmission speed is limited to a maximum of 655 Mbit/s within the specification. But that's not the limit. Through the unique processing of each semiconductor manufacturer, it is possible to achieve a high-speed transmission speed of about 3 Gbit/s.

The two differential signals, the positive electrode signal (A+) and the negative electrode signal (B−), are centered on a common voltage (Voc) of 1.2 V, and the two signals oscillate with a potential difference of 350 mV. Then, the differential of the oscilloscope is measured with a probe, and a signal waveform like Figure 2 is obtained. This is the amplitude difference between the two signals ((A+)−(B−)). By measuring with a differential probe, the amplitude difference can be calculated. But such a signal waveform does not exist physically.

The basic structure of the transmitter and receiver of LVDS is shown in the figure below. It uses two wires (i.e., differential signal lines) to transmit a single signal, and is driven by a constant current source, i.e., current-driven (as opposed to voltage-driven levels such as TTL and CMOS).

Among them, the field effect transistor in the driver (not necessarily the field effect transistor, because the LVDS technical specification mainly focuses on the electrical, interconnection and line termination of the LVDS interface, and there are no clear requirements for the production process, transmission medium and power supply voltage, that is, it can be realized by CMOS, GaAs or other processes, and the black cat and white cat that can catch mice are good cats) to form a full-bridge switch circuit. Used to control the current flow direction of the 3.5mA constant current source, a 100 ohm termination resistor is connected in parallel between the inverting and inverting terminals of the receiver, so that the current can generate voltage through the resistor, and then the high and low levels are formed by the receiver's judgment.

When Q2 and Q3 are on and Q1 and Q4 are cut-off, the constant current source current flows to the receiver through Q3, and goes down through the 100 ohm termination resistor and then returns to the driving end, and finally passes through Q2 to ground (GND), the current of 3.5mA produces a voltage drop of 350mV on the 100 ohm resistor, at this time, the voltage at the inverting terminal is higher than the voltage at the inverting terminal, and the output is a high level "H".

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CONTACT

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