MT61K256M32JE-14:A Original DRAM GDDR6 8G 256MX32 FBGA Memory Data Storage
Features
• VDD = VDDQ = 1.35V ±3%, 1.25V ±3%, and 1.20V –2%/+3%
• VPP = 1.8V –3%/+6%
• Data rate: 12 Gb/s, 14 Gb/s, 16 Gb/s
• 2 separate independent channels (x16)
• x16/x8 and 2-channel/pseudo channel (PC) mode configurations set at reset
• Single ended interfaces per channel for command/ address (CA) and data
• Differential clock input CK_t/CK_c for CA per 2 channels
• One differential clock input WCK_t/WCK_c per channel for data (DQ, DBI_n, EDC)
• Double data rate (DDR) command/address (CK)
• Quad data rate (QDR) and double data rate (DDR) data (WCK), depending on operating frequency
• 16n prefetch architecture with 256 bits per array read or write access
• 16 internal banks
• 4 bank groups for tCCDL = 3tCK and 4tCK
• Programmable READ latency
• Programmable WRITE latency
• Write data mask function via CA bus with single and double byte mask granularity
• Data bus inversion (DBI) and CA bus inversion (CABI)
• Input/output PLL
• CA bus training: CA input monitoring via DQ/ DBI_n/EDC signals
• WCK2CK clock training with phase information via EDC signals
• Data read and write training via read FIFO (depth = 6)
• Read/write data transmission integrity secured by cyclic redundancy check
• Programmable CRC READ latency
• Programmable CRC WRITE latency
• Programmable EDC hold pattern for CDR
• RDQS mode on EDC pins
DRAM | |
RoHS: | Details |
SGRAM - GDDR6 | |
SMD/SMT | |
FBGA-180 | |
32 bit | |
256 M x 32 | |
8 Gbit | |
1.75 GHz | |
1.3905 V | |
1.3095 V | |
0 C | |
+ 95 C | |
MT61K | |
Tray | |
Brand: | Original in stock |
Moisture Sensitive: | Yes |
Product Type: | DRAM |
Factory Pack Quantity: | 1260 |
Subcategory: | Memory & Data Storage |
Unit Weight: | 0.194430 oz |