CY2305SI-1H Wireless & RF Integrated Circuits Phase Locked Loops - PLL
■ 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
■ Zero input-output propagation delay
■ 60-ps typical cycle-to-cycle jitter (high drive)
■ Multiple low skew outputs
❐ 85 ps typical output-to-output skew
❐ One input drives five outputs (CY2305)
❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
■ Compatible with Pentium-based systems
■ Test Mode to bypass phase-locked loop (PLL) (CY2309)
■ Packages:
❐ 8-pin, 150-mil SOIC package (CY2305)
❐ 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
■ 3.3 V operation
■ Commercial and industrial temperature ranges
Phase Locked Loops - PLL | |
RoHS: | N |
Zero Delay PLL Clock Buffer | |
1 | |
10 MHz to 133.33 MHz | |
3.6 V | |
3 V | |
Si | |
- 40 C | |
+ 85 C | |
SMD/SMT | |
SOIC-8 | |
Height: | 1.48 mm |
Length: | 4.98 mm |
Moisture Sensitive: | Yes |
Operating Supply Voltage: | 3.3 V |
Product Type: | PLLs - Phase Locked Loops |
Series: | CY2305SI |
Factory Pack Quantity: | 2910 |
Subcategory: | Wireless & RF Integrated Circuits |
Width: | 3.99 mm |
Unit Weight: | 0.019048 oz |