MPC852TVR50A high quality Microprocessors MPU Ethernet 50 MHz Ethernet I2C SPI UART USB

Features

The following list summarizes the key MPC852T features:

• Embedded MPC8xx core up to 100 MHz

• Maximum frequency operation of the external bus is 66 MHz

— The 100MHz/80MHz core frequencies support 2:1 mode only

— The 50MHz/66MHz core frequencies support both 1:1 and 2:1 modes

• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32, 32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch, without conditional execution

— 4-Kbyte data cache and 4-Kbyte instruction cache

– 4-Kbyte instruction cache is two-way, set-associative with 128 sets

– 4-Kbyte data cache is two-way, set-associative with 128 sets

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks

– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis

— MMUs with 32-entry TLB, fully associative instruction and data TLBs

— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

• 32 address lines

• Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, flash EPROMs, and other memory devices

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte–256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

• Fast Ethernet controller (FEC)

• General-purpose timers

— Two 16-bit timers or one 32-bit timer

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture

• System integration unit (SIU)

— Bus monitor

— Software watchdog